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JA32050
8-Bit MCU,ADC,LCD Controller
Features
Operating Voltage: 2.4 V ~ 5.2V Stand-by Current=2uA @VDD=3V Operating Current = 2mA @ Fsys=2M VDD=3V, ADC off Built-in LCD driver: 4 COM * 20 SEG LCD duty option: 1/3 duty or 1/4 duty LCD bias option: 1/2 bias or 1/3 bias R-Bias or C-Bias for LCD by mask option RC oscillation for system clock (R external) External 32.768 KHz crystal for RTC Internal RC 32k for WDT or timer Internal with dual slope ADC and 3 OP amplifiers Internal with an 8-bit I/O port dedicated for ADC interface (Port A) Normal 8-bit I/O port for general I/O (Port B) with interrupt function Internal with two16-bit timers (TMR0, TMR1) Internal 8-bit WDT (watchdog timer) R/F circuit available (PB0, PB1) 7K bytes of Program ROM 128 bytes of data RAM STOP and HALT mode for power saving Low battery detect AVdd source current 20 mA AVdd and Vdd separated
General Description
The JA32050 incorporates an 8-bit MCU, ADC, LCD controller, timers, WDT, 8 programmable general I/Os and R/F circuits inside. It is designed for measuring application, especially suitable for pressure related product such as manometer.
Block Diagram
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Pad Assignment
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 Pad Name SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VDD VCC VPP OP1P OP1N X 70.00 70.00 70.00 70.00 70.00 70.00 70.00 70.00 70.00 70.00 70.00 70.00 Y 1866.18 1755.98 1645.78 1535.58 1425.38 1315.18 1204.98 1085.47 969.06 849.00 738.80 628.60 Pad No. 13 14 15 16 17 18 19 20 21 22 23 24 Pad Name OP1O OP2O OP2N OP2P OP3P OP3N OP3O REF1 VSS RR RC CC X 70.00 70.00 124.30 234.50 344.70 454.90 613.46 779.94 890.14 1000.34 1110.54 1262.95 Y 455.30 327.40 70.00 70.00 70.00 70.00 70.00 70.00 70.00 70.00 70.00 70.00
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Pad No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Pad Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 SC PDET VDD OSCI VSS RESB XT1 XT2 COM3 X 1419.58 1529.78 1639.98 1750.18 1860.38 1970.58 2003.58 2003.58 2003.58 2003.58 2003.58 2003.58 2003.58 2003.58 2003.58 2003.58 2003.58 Y 70.00 70.00 70.00 70.00 70.00 70.00 344.96 455.16 588.93 724.48 834.68 944.88 1055.08 1165.28 1275.48 1385.68 1508.88 Pad No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Pad Name COM2 COM1 COM0 VLCD SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 X 2003.58 1974.44 1864.24 1754.04 1643.84 1533.64 1423.44 1313.24 1203.04 1092.84 982.64 872.44 762.24 652.04 541.84 431.64 321.44 Y 1619.08 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38 1893.38
Chip Size : 2073.58 x 1963.38( m)2
Pin Descriptions
Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TEL
Pad Name SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VDD AVDD VPP OP1P OP1N OP1O OP2O OP2N OP2P OP3P OP3N OP3O REF1 VSS RR RC CC PB7
I/O O O O O O O O O O I I I O O I I I I O O -- I I O I/O
FAX
Description Segment 6 Segment 5 Segment 4 Segment 3 Segment 2 Segment 1 Segment 0 Positive power supply Analog power supply (ON/Off by PA5) Sensor power supply (SPWR) OP1 "+" input OP1 "-" input OP1 output OP2 output OP2 "-" input OP2 "+" input OP3 "+" input OP3 "-" input OP3 output For reference voltage input Negative power supply or GND 2nd stage of internal amplifier 2nd stage of OPA negative input end 2nd stage of OPA output end PB I/O pin 7 19-3
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PB6 PB5 PB4 PB3 PB2 PB1 PB0 SC PDET VDD OSC VSS RESB X1 X2 COM3 COM2 COM1 COM0 VLCD SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 I/O I/O I/O I/O I/O I/O I/O I/O I O -- -- I I I O O O O I O O O O O O O O O O O O O PB I/O pin 6 PB I/O pin 5 PB I/O pin 4 PB I/O pin 3 PB I/O pin 2 PB1: normal I/O pin 1 or RS, RF control pin PB0: normal I/O pin 0 or RS, RF control pin R/F output pin, connected to MCU TMR pin Low battery detect input Positive power supply Oscillator generator I/O pins Negative power supply or GND System reset input, low active 32.768k Hz crystal input 32.768k Hz crystal input Common 3 of LCD Common 2 of LCD Common 1 of LCD Common 0 of LCD LCD panel bias voltage Segment 19, in C bias mode, this pin will be CAP2 Segment 18, in C bias mode, this pin will be CAP1 Segment 17, in C bias mode, this pin will be V30 Segment 16, in C bias mode, this pin will be V15 Segment 15 Segment 14 Segment 13 Segment 12 Segment 11 Segment 10 Segment 9 Segment 8 Segment 7
Electrical Characteristics
Symbol VDD IDD ISTB1 ISTB2 RPH IOH1 IOL1 IOH2 IOL2 IOL3 Parameter Operating Voltage Operating Current Standby Current Standby Current Pull high resistor PB0, PB1 Source Current PB0, PB1 Sink Current PB2 PB7 Source Current PB2 PB7 Sink current SC sink current 3V 3V 3V 3V 3V 3V 3V 3V 3V No Load, Fsys=2MHz Fsys OFF, 32K ON Fsys OFF, 32K OFF PB0 - PB7 VOH1=2.7V VOL1=0.3V VOH1=2.7V VOL2=0.3V VOL3=0.3V 20 20 1 1 20 Test Condition VDD Condition Min.. 2.2 Typ. 3.0 2 3 1 100 30 30 3 3 30 Max. 5.2 3 5 3 k mA mA mA mA mA Unit V mA A A
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IOL4 IOH3 LCD COM, SEG Sink Current LCD COM, SEG Source Current 3V 3V VOL4=0.3V VOH2=2.7V 80 50 150 80 A A
MCU Function Description
JA32050 contains a 6502 based 8-bit Micro-Controller Unit (MCU) with Program ROM, Special register, user data RAM and two 16-bit Timers inside. This chip also provides multi external interrupt pins (I/O Port B) and Low Voltage Detector (LVD) function.
Memory
Memory Mapping Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h-1Fh 21h 22h 23h 24h 80h ~ FFh 200h ~ 213h E400h ~ FFFFh Definition POWERC (R/W) INTC (R/W) INTF (R/W) WDTCLR (W) WDTC (R/W) TMR0H (R/W) TMR0L (R/W) TMR0C (R/W) TMR1H (R/W) TMR1L (R/W) TMR1C (R/W) PA (R/W) PAC (R/W) PAR (R/W) PB (R/W) PBC (R/W) PBR (R/W) Reserved CON0 Reserved LCD0 LCD1 General purpose Data Memory & Stack LCD data RAM User Program
Data RAM Total 128 bytes of Data RAM (including the stack) are available from $80h to $FFh. Program ROM Total 7K bytes of user ROM located from $E400h to $FFFFh are available. Reset & Interrupt Vector The reset vector is located at $FFFCh, and interrupt vector followed. Stack Pointer The stack pointer is set from $FFh after power on.
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Power Configuration
POWERC Register Address POWERC 00h Bit7 LVFLAG Bit6 DETEN Bit5 -- Bit4 STOP Bit3 -- Bit2 -- Bit1 -- Bit0 HALT
The system provides the HALT mode and the STOP mode for power saving: HALT mode Writing "1" to the HALT bit cause system enter HALT mode. In HALT mode, the system clock stop running but the internal RC clock (32K) continuously keeps free running. The timer overflow, WDT overflow, external interrupt (INTB) or PA,PB change state can wakeup the system to leave the HALT mode. The HALT bit will be cleared to "0" automatically when system is awakened (STOP bit unchanged). STOP mode Writing " 1" to the STOP bit causes system enter STOP mode. In STOP mode, both the system clock and internal RC clock stop running. External interrupt (INTB) or PA,PB change state can wakeup the system. The HALT bit and the STOP bit will be cleared to "0" automatically when system is awakened. Low voltage Writing " 1" to DETEN bit enable the low battery detector circuit of the system. If the low battery situation is detected, the LVFLAG bit will be set to "1" by detector circuit. After writing the DETEN bit, the user must insert 2 NOP instructions in the program before program reading the LVFLAG data. External resistor shown below adjusts the low voltage level:
The table below is a reference for low voltage setting. If user set low voltage level at 2.15V then 40K ohm resistor shall be used. When Vdd drops to 2.15V the LVFLAG will become "1" indicating the low battery event. Resistor Vdd PDET LVFLAG 40 K 2.15V 0.699V 1 50 K 2.45V 0.899V 1 54 K 2.55V 0.97V 1 60 K 2.65V 1.09V 1 70 K 2.85V 1.27V 1
Reset and Wakeup
The system will be reset by the following conditions: Power on Reset pin activated (Low) Illegal address generation WDT overflow VDD voltage lower than 1.8V
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The system will be awakened from STOP mode or HALT mode by the following conditions: Timer/WDT overflow Level changes on PB input pins The above situations will make system start running. The starting address depends on the INTF register setting. If the global interrupt bit (INTE) is cleared and the corresponding interrupt bit is set, no wakeup interrupt will be generated and program start running from next instruction in STOP mode or HALT mode. If the global interrupt bit (INTE) is set, the system will execute the corresponding interrupt service routine first then back to execute the next instruction in STOP mode or HALT mode.
Interrupt
In JA32050, the INTC register and the INTF register handle the interrupt operation. Setting or clearing the INTC (interrupt control register) bits will enable or disable the interrupt function. The INTF (interrupt flag) shows the current interrupt status. The system will be interrupted by the following conditions: Timer/WDT overflow Level changes on PB input pins Interrupt control register (INTC) definition is shown below: INTC (R/W): 01h Register Bit No. 0 1 2 3 4 5 6 7
Label INTE Reserved TMR0 TMR1 PAI PBI
INTC
Function Global interrupt enable bit (1= Enabled; 0 = Disabled) Must be set to "0" TMR0 interrupt Enable bit (1= Enabled; 0 = Disabled) TMR1 interrupt Enable bit (1= Enabled; 0 = Disabled) Port A change state interrupt Enable bit (1= Enabled; 0 = Disabled) Port B change state interrupt Enable bit (1= Enabled; 0 = Disabled) Reserved Reserved
Interrupt Flag (INTF) definition is shown below: INTF (R/W): 02h Register Bit No. 0 1 INTF 2 3 4 5 6 7 Label INTF TMR0F TMR1F PAF PBF Function External INT interrupt flag bit (1= Active; 0 = Inactive) TMR0 timer interrupt flag bit (1= Active; 0 = Inactive) TMR1 timer interrupt flag bit (1= Active; 0 = Inactive) Reserved Port A change state interrupt flag bit (1= Active; 0 = Inactive) Port B change state interrupt flag bit (1= Active; 0 = Inactive) Reserved Reserved 19-7
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Timers and WDT
The JA32050 contains two16-bit timers (TMR0, TMR1) and one watchdog timer (WDT). The registers related to timers are TMR (timer content) and TMRC (timer control). TMR0 (05h,06h) & TMR0C (07h) The TMR0 is a 16-bit count-up counter. The clock source may come from system clock (Fsys/4), internal RC clock, external pulse input (SC) or external 32k crystal. The default value of the control register TMR0C is 00. The definition of TMR0C is listed as following: Labels TON0 (TMR0) TS2, TS1, TS0 TMR/WDT Bits 0 3-1 4 5 Function Timer0 enable/disable definition bit 0 = Disable; 1 = Enable Timer clock rate selection bits (prescale) Reserved
To assign pre-scale counter to Timer0 or WDT 0: Timer 1: WDT TM1, TM0 7, 6 To define the operation mode 00= Timer mode (system clock/4) 01= Timer mode (internal RC clock) 10= Event count mode from external SC pin 11= Timer mode (32.768k Hz crystal) Both TMR0 and WDT share with an 8-bit prescaler. If the prescaler is assigned to TMR0, the WDT clock will be 1:1 to the clock source (no prescale function), vice versa. The ratio table is shown below: TS2 0 0 0 0 1 1 1 1 TS1 0 0 1 1 0 0 1 1 TS0 0 1 0 1 0 1 0 1 TMR Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
TMR1 (08h, 09h) & TMR1C (0Ah) The TMR01is a 16-bit count-up counter. The clock source may come from system clock, internal RC clock, external pulse input or external 32k crystal. The default value of the control register TMR1C is 00. The definition of TMR0C is listed as following: Labels Bits Function TON1 0 Timer1 enable/disable definition bit 0 = Disable; 1 = Enable TS2, TS1, TS0 3-1 Timer clock source selection bits 4 Reserved TMROUT TM1, TM0 5 7, 6 This bit has to be set to "0"; SC is configured as input pin. To define the operation mode 00= Timer mode (system clock/4) 01= Timer mode (internal RC clock) 10= Event count mode from External SC pin 11= Timer mode (32.768k crystal)
There is an 8-bit prescaler dedicated to TMR1. The ratio table is shown below:
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TS2 0 0 0 0 1 1 1 1 TS1 0 0 1 1 0 0 1 1 TS0 0 1 0 1 0 1 0 1 TMR1 Clock Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Watchdog Timer The clock source for watchdog timer (WDT) can be either internal RC (32kHz) or system clock/4; decided by Bit 4 of WDTC register. When WDT is enabled, user shall reset (writing "1") Bit 0 of WDTCLR register within a specific time to prevent WDT overflow. WDTCLR (W): 03h Bit7 Bit6 -- -- WDTC (R/W): 04h Bit7 Bit6 -- -- Bit5 -- Bit5 -- Bit4 -- Bit4 WDTCLK Bit3 -- Bit3 -- Bit2 -- Bit2 -- Bit1 -- Bit1 -- Bit0 CLRWDT Bit0 WDTEN
Bit 4 (WDTCLK): Select the WDT clock source 0=system clock/4 (Default) , 1= Internal RC clock Bit0 (WDTEN): To enable/disable the WDT, 0= Disable (Default), 1= Enable
I/O Configuration
The I/O port A (PA) is dedicated to ADC circuit so that user cannot use PA for other use. Port B (PB) can be used as normal input and output operations. For input operation, PB is non-latched , for output operation, all the data are latched and remain unchanged till the output latch is re-written. Each I/O port has its own control register (PAC, PBC) to control the input/output configuration. PA Configuration PA control register specifies the characteristic of PA. Please refer to the table below: Label Address Function PA 0Bh PA data input/output PAC 0Ch PA direction control, 1=input 0=output PAR 0Dh PA pull-high resistor option, 1=With, 0=Without
R/W R/W R/W R/W
Default FF FF FF
In JA32050, PA is dedicated to ADC circuit, PA5 for ON/OFF control, PA6 for COMPO, PA4 for CHAR/DIS (charge/discharge) control, others PA pins cannot be used. Please see the block diagram on first page for reference. PB Configuration For port B, they can be configured as follows: Label Address Function PB 0Eh PB data input/output PBC 0Fh PB direction control, 1=input 0=output PBR 10h PB pull-high resistor option, 1=With, 0=Without
R/W R/W R/W R/W
Default FF FF FF
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R/F Function Descriptions
PB0, PB1 of port B can be configured (mask option) to perform either R/F function or normal I/O function. In R/F application, user put reference resistor (R1) to PB0, sensor to PB1 (interchangeable). One capacitor also used to from the RC oscillation loop. Please see the following figure for reference:
To active R1, MCU output high signal to PB0 and output low signal to PB1at the same time. Signal can be generated on the SC pin. Inside the JA32050, the signal on SC pin can be routed to the clock source of timer by programming. The R/F circuit will be activated only when timer in event count mode ("10" for TM1, TM0).
LCD Function Descriptions
LCD Clock The clock source for LCD can be internal RC (32kHz), external 32k crystal or system clock; decided by Bit 5, Bit 4 of CON0. The Bit 3 of CON0 controls the LCD on/off, "1" for LCD on, "0" for LCD off. CON0 (R/W): 21h B7 B6 B5 B4 B3 B2 B1 B0 -- -- OSC1 OSC0 LCD -- -- -- OSC1, OSC2: 00 internal RC 32k 01 internal RC 32k 10 external 32k 11 system clock Note: The STOP mode and the HALT mode will affect the LCD display. In STOP mode, the LCD
cannot show any message because all clock are disabled. In HALT mode, message
can be seen on the LCD if the clock source is internal RC or external RC. LCD Common & Segment If user chooses R bias for the LCD, the segment will be SEG 0 to SEG 19. If user chooses C bias for the LCD, the segment will be SEG 0 to SEG 15. The user can configure LCD controller to 3 COM or 4 COM; decided by Bit 6, Bit 5, and Bit 4 of LCD0. The Bit 7 of LCD0 controls frame frequency of LCD, "1" for 170 Hz on, "0" for 85 Hz. Please see the table below: LCD0 (R/W): 23h B7 B6 B5 B4 B3 Frame C2 C1 C0 -- Frame: 0 - 85 Hz 1 - 170 Hz C2, C1, C0: (1, 0, 0): 3 COM, (0, 1, 1): 4 COM B2 -- B1 -- B0 --
LCD Bias The user can configure LCD controller to 1/2 bias or 1/3 bias; decided by Bit 2, Bit 1, and Bit 0 of LCD1.
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LCD1 (R/W): 24h B7 B6 B5 B4 B3 B2 -- -- -- -- -- B2 B2, B1, B0: (1, 0, 0): 1/2 bias, (0, 1, 1): 1/3 bias. B1 B1 B0 B0
LCD Data RAM The RAM is located from 200h to 213h. Please refer to the table below, "*" means "don't care". RAM Address Segment number Content 200h Seg0 *,*,*,*,COM3,COM2,COM1,COM0 201h Seg1 *,*,*,*,COM3,COM2,COM1,COM0 202h Seg2 *,*,*,*,COM3,COM2,COM1,COM0 203h Seg3 *,*,*,*,COM3,COM2,COM1,COM0 204h Seg4 *,*,*,*,COM3,COM2,COM1,COM0 205h Seg5 *,*,*,*,COM3,COM2,COM1,COM0 206h Seg6 *,*,*,*,COM3,COM2,COM1,COM0 207h Seg7 *,*,*,*,COM3,COM2,COM1,COM0 208h Seg8 *,*,*,*,COM3,COM2,COM1,COM0 209h Seg9 *,*,*,*,COM3,COM2,COM1,COM0 20Ah Seg10 *,*,*,*,COM3,COM2,COM1,COM0 20Bh Seg11 *,*,*,*,COM3,COM2,COM1,COM0 20Ch Seg12 *,*,*,*,COM3,COM2,COM1,COM0 20Dh Seg13 *,*,*,*,COM3,COM2,COM1,COM0 20Eh Seg14 *,*,*,*,COM3,COM2,COM1,COM0 20Fh Seg15 *,*,*,*,COM3,COM2,COM1,COM0 210h Seg16 *,*,*,*,COM3,COM2,COM1,COM0 211h Seg17 *,*,*,*,COM3,COM2,COM1,COM0 212h Seg18 *,*,*,*,COM3,COM2,COM1,COM0 213h Seg19 *,*,*,*,COM3,COM2,COM1,COM0
LCD R bias / C bias
LCD can be configured as R bias or C bias. In R bias, Seg0-Seg19 all can be used. In C bias, only Seg0-Seg15 can be used. The circuit for LCD interface will be little different in different Vdd and LCD bias when using capacitor for LCD biasing (C bias). Please see the table below: Vdd = 3 V 1/2 bias 1/3 bias Vlcd V30 Connected to Vdd Connected to Vdd or open Connected to Vss Connected to Vdd through a 104 cap V15 CAP1, CAP2 Connected to Vss CAP1 connected to through a 104 cap CAP2 through a 104 cap Connected to Vss CAP1 connected to through a 104 cap CAP2 through a 104 cap
Vdd = 4.5 V 1/2 bias Vlcd V30 Connected to Vdd Connected to Vdd or open V15 CAP1, CAP2 Connected to Vss CAP1 connected to through a 104 cap CAP2 through a 104 19-11
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1/3 bias Connected to Vdd Connected to Vdd through a 104 cap cap Connected to Vss CAP1 connected to through a 104 cap CAP2 through a 104 cap
In R bias application, V30, V15, CAP1, CAP2 are normal segment signals.
ADC Function Description
ADC General The JA32050 offers very high accuracy A/D conversion by using Dual Slope integration. It incorporates operational amplifiers, comparators, power on/off control circuit and charge/discharge control circuit inside to achieve high performance for application. A voltage follower was used as buffer for sensor signal input. Because of the buffer's great isolating characteristic, the signal from sensor will be precisely duplicated and sent out at output pin without any distortion. An operational amplifier was designed for user to properly amplify the sensor signal from buffer. Inside the chip, a current accurately proportional to the amplified signal level will be generated to charge an external RC network for a fixed time interval. After being charged for this interval, the capacitor is discharged by a constant current until the voltage reaches 1/6 VDD. This discharging time is proportional to the input signal level and is used by external controller to enable a counter; the final count is proportional to the input level and can be converted to digital output. Because the charge cycle and discharge cycle go through the same RC network, using a high quality capacitor is recommended. ADC Timing Diagram
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Application Diagram
The application diagram shown below is a simple illustration for using the JA32050 chip. It shall be noted that inside the JA32050, PA is dedicated to ADC circuit ( PA5 for ON/OFF control( PA6 for COMPO, PA4 for CHAR/DIS control). Vdd:3 V and C type 1/3 bias were used in this application.
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The application shown below uses R type bias for LCD biasing. All segments (SEG0 - SEG19) can be used.
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Note:
a. b. c. d. e. Pin 8 VDD shall be connected to power supply input. Pin 9 AVDD is the voltage output controlled by PA5. Pin 10 VPP is a voltage input pin used for sensor power supply and OP operation. If no voltage regulation for VPP is needed, connect AVDD to VPP. If VPP needs a regulated voltage level, use AVDD as the input voltage to an external regulator then connects the output of the regulator to the VPP.
Application Introduction
The circuit above was designed for multi function application. It handles two sensors of different functions. Sensor 1 can be pressure related type sensor such as sensors for manometer or sphygmomanometer application. Sensor 2 is the kind of sensor that output different resistance when the outside environment changes such as temperature sensor. Please see the following introduction for reference: a. System Clock: External RC oscillation was used to generate the system clock. The OSC was connected to Vdd through a 150 k ohm resistor; the system clock will be around 4 MHz. b. 32.768 k Crystal: This crystal used to generate real time clock. c. Sensor 1: The ADC circuit was used by sensor 1. Sensor 1 can be pressure related type sensor such as sensors for manometer, sphygmomanometer application. d. OP gain: R2, R3 decides the OP gain. e. Charge/Discharge circuit: R3, C forms the charge/discharge path. f. REF1, REF2: capacitors were connected to filter the noise. g. R4: used for low voltage detect. h. Sensor 2: R/F circuit was used by sensor 2. The reference resistor R5 was connected to PB1. i. General I/O: PB2 - PB7 reserved for general I/O j. LCD: COM0-COM3, SEG0-SEG15 were used for LCD interface. k. LCD C bias type: In this application, C bias was used so the V15, CAP1, CAP2 shall need capacitor for C type bias. l. Vlcd & V30: In this application Vdd = 3 V, and 1/3 bias was used for LCD, the V30 shall be connected to Vdd and Vlcd needs a capacitor to Vss.
Programming Example
The following program is an example for JA32050 programming. It demonstrates how MCU controls the ADC circuit. This program also shows users the way to configure the JA32050. User can learn some programming skills listed below: a. Program format b. Assign program memory location c. PA, PB configuration d. Timers enable/disable e. ADC control f. Interrupt routine handle
; ;
;--------------------------------------------------------------; This is an example program for JA32050 programming ;--------------------------------------------------------------;I/O port description: ;PA0-PA7 for ADC control(COMPO,ON/OFF,CHR) ;PB0-PB3 for press key ; ;Main program brief description ;a. MCU set up internal registers
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;b. MCU enable timer0 and asserts CHR(charge) signal to inform ADC starts charging ;c. MCU disable timer0 and asserts DISC signal to inform ADC starts discharging ;d. MCU enables timer1 to count discharge time simultaneously ;d. ADC asserts COMPO low when CC reaches 1/6 Vdd ;e. MCU stop timer1 counting when COMPO low detected ;f. Timer1 content was ready to read out ;---------------------------------------------------------------; MCU internal register address definition POWERC INTC INTF WDTCLR WDTC TMR0L TMR0C TMR1L TMR1C PA PAC PAR PB PBC PBR CON0 LCD0 LCD1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 = ;;$00 = $01 = $02 = `;$03 = $05 = $06 = $07 = $09 = $0a `'' = `'$0b ; ADC control = ``$0c `'= `'$0d ;'= `'$0e ;'= ``$0f '= `''`'$10 `'''= ' $21 `''= `'$23 `' `'= `'' `'`$24 = $200 = $201 = $202 = $203 = $204 = $205 = $206 = $207 = $208 = $209 = $20a = $20b = $20c
;================================================== ; General purpose data memory & stack ;================================================== Temp = $e0h DELAY = Temp+1 COUNT = DELAY+1 Timer1_h = COUNT+1 ;=============================================== ; ;Program located from $e400 ; org $e400
Preliminary
TEL 886-3-5770755 FAX 886-3-5770756
19-16
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Ver.0.0
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JA32050
START: cld clc clv cli lda sta sta sta lda sta lda sta ;clear decimal flag ;clear carry flag ;clear overflow flag ;clear interrupt disable flag, allow MCU accept INT ;clear timer0 high byte ;clear timer0 low byte ;clear timer1 low byte ; ; ; ` ;"0000,1110" TMR clk rate= 1:256 ,timer disable ;;initial for TMR0 ;"0000,0100" TMR clk rate= 1:8 ,timer disable ;; initial for TMR1 ;initial stack pointer address from $FF ;;copy x register value to stack pointer ; `; ;"0100,0000"configure PA6 as input port ;"1111,0000" PA4-PA7 pull-high resistor
; #$00 TMR0H TMR0L TMR1L #$0e TMR0C #$04 TMR1C
ldx #$ff txs lda sta lda sta lda sta lda sta sta lda sta #$40 PAC #$f0 PAR #$00 PA #$0f PBR PBC #$ff PB
;;;"0000,0000" ; ;; ;PA0-PA7 , output low ;configure PB0-PB3 as input port, PB4-PB7 as output
;;PB4-PB7 output high ;LCD initial and clear ; LCD clock source: internal 32k clock, LCD "on" ; CON0 bit 7 was not used for real chip ; LCD: 3 common, LCD0 bit0-bit2 was not used for real chip ; LCD: 1/2 bias
LCD_INIT: lda #$88 sta CON0 lda #$46 sta LCD0 lda #$04 sta LCD1 jsr LCD_CLEAR ON_OFF: lda #$20 ora PA sta PA CHARGE_HI: lda #$10 ora PA sta PA TMR1_ON: lda #$01 ora TMR1C ;;
;"0010,0000",enable ADC
; ; ;"0001,0000",output CHARGE high
; ; enable timer0 for charge time
Preliminary
TEL 886-3-5770755 FAX 886-3-5770756
19-17
E-mail sales@jaztek.com.tw
Ver.0.0
Web-site www.jaztek.com.tw
JA32050
sta TMR1C CHARGE_TIME: lda TMR0L ; ;;;;charge time loop; leave the loop when time up cmp #$b0 bne CHARGE_TIME TMR1_OFF: lda #$fe and TMR1C sta TMR1C lda sta #$00 TMR1L ; charge done, disable the timer0 "1111,1110"
;; clear timer1 content for next charging
DISCHARGE_ON: lda #$ef and PA sta PA TMR0_ON: lda #$00 sta TMR0L sta TMR0H lda #$01 ora TMR0C sta TMR0C COMPO: lda #$40 WAIT: bit PA bne WAIT
;"1110,1111", assert low signal to start discharging
; clear timer0 content ; enable timer0 for discharge time counting
;"0100,0000" ;checking if PA6 is zero or not
TMR0_OFF: lda #$fe ; charge done, disable the timer1 "1111,1110" and TMR0C sta TMR0C jsr DLY1 jmp CHARGE_HI ;run again ;----------------------------------------LCD_CLEAR: lda #$00 ldx #$00 ldy #$0e ; ;14 times NEXT_BYTE: sta SEG0,x inx dey bne NEXT_BYTE rts ;---------- subroutine DLY1 -----------DLY1: lda #$ff sta DELAY ; DELAY = 256
Preliminary
TEL 886-3-5770755 FAX 886-3-5770756
19-18
E-mail sales@jaztek.com.tw
Ver.0.0
Web-site www.jaztek.com.tw
JA32050
sta COUNT ; COUNT = 256 Loop1: nop nop dec COUNT bne Loop1 nop ; now count = 0 nop dec DELAY bne Loop1 rts ;------------------------------------;Interrupt service routine ;-------------------------------------INTHANDLE: sei pha php lda bit bne lda bit bne ; ;disable INT ;; ;push A register ;; ;push status register
#$02 INTF ;; timer0 INT? TIMER0_INT ; timer0 #$04 INTF ;; timer1 INT? TIMER1_INT ; timer1
TIMER0_INT: lda #$fd ; ;"1111,1101", clear timer0 flag and INTF sta INTF jmp INT_RTN TIMER1_INT: lda #$fb ;"1111,1011", clear timer1 flag and INTF sta INTF inc timer1_h ; ; add carry jmp INT_RTN INT_RTN: plp ;pop status register pla ;pop A register cli ; ;enable INT rti ;-------------------------------------org $fffc dw START ;FFFC - FFFD : store program start address dw INTHANDLE ; ;FFFE - FFFF : store interrupt subroutine address ends end
Preliminary
TEL 886-3-5770755 FAX 886-3-5770756
19-19
E-mail sales@jaztek.com.tw
Ver.0.0
Web-site www.jaztek.com.tw

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